Nvidia Drive PX 2 Uses Integrated and Discrete Pascal GPU Cores - 24 DL TOPS, 8 TFLOPs and Up To 4GB GDDR5 [Updated]

Nvidia's GTC 2022 result is going on as we speak and the company has revealed quite a few details about its upcoming Drive PX ii board which will be the flagship SKU for the car and autonomous industry. The board volition feature both integrated and discrete Pascal GPUs on lath for a peak performance of 24 DL TOPS or 8 TFLOPS.

Nvidia demos Drive PX 2 at GTC 2022 - features a CPU/GPU complex with integrated and dedicated Pascal cores

Lets start with the basic specifications. Nvidia is claiming tiptop functioning of 8 TFLOPs (FP32) and up to 24 DL TOPS. While I am certain the first metric is familiar, the 2d is one of Nvidia's own blueprint and refers to "Deep Learning - Tera-Operations Per Second". This means that the Drive PX ii can do 24, 000,000,000,000 deep learning operations per second. This is a pretty huge number and because that the automobile industry volition exist leaning more than and more heavily on DNNs for auto-pilot and autonomous driving applications - this is an important number.

Moving on, the CPU complex of the Drive PX two board is every bit follows: There are 2 Denver2 cores present plus 4x Cortex A57 cores. The architecture used is ARM v8 64 fleck. The CPU Circuitous will have upto 8 GB of LPDDR4 memory (UMA) with up to 50 GB/s bandwidth. Nvidia'due south 5th generation compages, aka Pascal, features custom acceleration for deep learning and the detached GPUs present will have up to lxxx GB/southward of bandwidth.

Each CPU complex will have access to its own integrated Pascal Cores (as well as a dedicated Pascal GPU over PCIe) and will exist connected by a i Gb Ethernet connection. The discrete Pascal cores will have upwards to 4GB of GDDR5 retentivity (each) and will characteristic approximately 80 GB/s of bandwidth - which tells us that we are probably looking at depression end (or custom) cores around the GP106 spectrum. They apply a 128-chip interface that connects to four GDDR5 memory fries clocked at 1.25 GHz. The clock can go as high as 1.five GHz for a total of 96 GB/south.

The Pascal cores used on the Drive PX 2 has a specialized instruction set up that is designed to accelerate DNN performance on the go . The interface itself (of the PX 2 board) supports an IO of lxx Gigabits per 2d. Interestingly, Nvidia has put a lot of thought on redundancy and mission disquisitional organization safety. An ASIL-D safe micro controller is as well present on the board itself. Not only that, just the hardware is AutoSAR compliant, and designed from the ground up to permit devs to take full advantage of the resources on the lath.

NVIDIA Drive PX Generation Comparing:

Product Name	NVIDIA Drive PX	NVIDIA Drive PX 2	NVIDIA Drive Xavier	NVIDIA Bulldoze Pegasus	NVIDIA Drive AGX Orin
SOC Name	Tegra X1	Parker	Xavier	Xavier	Orin
Process Engineering	20nm SOC	16nm FinFET	12nm FinFET	12nm FinFET	TBA
SOC Transistors	ii Billion (Tegra X1)	Due north/A	7 Billion (Xavier)	7 Billion (Xavier)	17 Billion (Orin)
GPU Architecture	Maxwell (256 Cadre)	Pascal (256 Cadre)	Volta (512 Core)	Volta (512 Cadre)	Ampere?
CPU	16 Core ARM CPU	12 Core ARM CPU	8 Core ARM CPU	16 Core ARM CPU	12 Core ARM CPU
CPU Compages	8x Cortex A57 8x Cortex A53	4x Denver 8x Cortex A57	Carmel ARM64 8 Core CPU (8 MB L2 + four MB L3)	Carmel ARM64 8 Cadre CPU (8 MB L2 + four MB L3)	ARM Herclues Cores
Compute DLTOPs	N/A	20 DLTOPs	30 TOPs	320 TOPs	200 TOPs
Total Chips	two x Tegra X1	two x Tegra X2 2 ten Pascal MXM GPUs	i x Xavier	2 ten Volta two ten Turing	1 ten Ampere
Organization Memory	LPDDR4	8 GB LPDDR4 (fifty+ GB/s)	16 GB 256-chip LPDDR4	LPDDR4 + GDDR6	Northward/A
Graphics Retentivity	N/A	4 GB GDDR5 (80+ GB/southward)	137 GB/south	1 TB/s	200 GB/southward
TDP	20W	80W	30W	500W	TBA

Nvidia'south concluding financials indicated a very potent growth of their automotive department. The reason is of course that their Tegra chips are increasingly in need as the ultimate pick to power digital cockpit systems for diverse automobile vendors. Nvidia has also been aspiring to break into the ADAS business concern with its new Bulldoze PX chip. Infact, Elon Musk was present at CES this year when the CEO of Nvidia demonstrated the capabilities of the Drive PX board. This acquired many to speculate that the board was nowadays within the Tesla models. This is even so, not true , and you lot would be forgiven for thinking that the latest Tesla vehicles incorporate the module.

Nvidia'due south previous generation of Tegra GPUs simply powered the infotainment cluster aboard cars like the Tesla. Information technology is credible however, that Nvidia aims to modify this with its successive designs - each full-bodied on providing more and more power for DNN-based autonomous capabilities. In fact, the Bulldoze PX2 board has already shipped to Tier 1 customers for an estimated price tag of $15000. That might audio like a steep cost for a calculator board, but considering how much a LIDAR based DNN organization with bodily dGPUs cost - this number amounts to mere pennies.